WTF am I doing wrong with this sub osc circuit

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abelovesfun
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WTF am I doing wrong with this sub osc circuit

Post by abelovesfun »

As part of a future module, i thought it would be fun to include some classic sub octave fun, so I looked around and found this SH101 circuit:
Image
No need to reinvent the wheel, so I added it here:
Image
I can see and hear the -2 octave square and pulse waved, but I get nothing out of the sub octave (pin 13). I see the clock coming in at pin 11 just fine.
What am I doing wrong? I thought these CD chips were dead easy.
Much thanks for any help you can provide.
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emmaker
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Re: WTF am I doing wrong with this sub osc circuit

Post by emmaker »

Did you put power on the 4013's pins 14 and 7?
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Re: WTF am I doing wrong with this sub osc circuit

Post by guest »

ive had issues with self-clocking. the input pulse comes in, an output pulse is generated, but due to high impedance of the input stage the output pulse is capacitively coupled back to the input, resetting the output. so you get these submicrosecond pulses that are barey visible. try buffering with an emitter follower to drive the input and see if that helps.
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Re: WTF am I doing wrong with this sub osc circuit

Post by Elahrairah »

guest wrote: Thu May 12, 2022 8:34 pm ive had issues with self-clocking. the input pulse comes in, an output pulse is generated, but due to high impedance of the input stage the output pulse is capacitively coupled back to the input, resetting the output. so you get these submicrosecond pulses that are barey visible. try buffering with an emitter follower to drive the input and see if that helps.

That's a good explanation, I had some weirdness unexplained on the 4013 solved by putting a 1k resistor between the components, here pin 12 to pin 3, which 'slowed down' the signal enough to stabilize behavior.
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Re: WTF am I doing wrong with this sub osc circuit

Post by guest »

thats a good suggestion to slow things down a bit. sometimes the problems are worse on a protoboard versus pcb, as the capacitance between pins is higher due to the protoboard internal bussing structure.
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Re: WTF am I doing wrong with this sub osc circuit

Post by abelovesfun »

Elahrairah wrote: Thu May 12, 2022 8:44 pm
guest wrote: Thu May 12, 2022 8:34 pm ive had issues with self-clocking. the input pulse comes in, an output pulse is generated, but due to high impedance of the input stage the output pulse is capacitively coupled back to the input, resetting the output. so you get these submicrosecond pulses that are barey visible. try buffering with an emitter follower to drive the input and see if that helps.

That's a good explanation, I had some weirdness unexplained on the 4013 solved by putting a 1k resistor between the components, here pin 12 to pin 3, which 'slowed down' the signal enough to stabilize behavior.
You mean Pin 13 to Pin 3, right? Added a 1k between those pins, but still no dice :( Appreciate the effort though!
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Re: WTF am I doing wrong with this sub osc circuit

Post by Synthiq »

Flip-flops can have problems with slow rise and fall times on the clock input so a ramp input isn't the best input signal. You can try the pulse output instead to see if it solves the problem. As an alternative, you can use the first two outputs from a 4024 or 4040 instead as these chips has Schmitt-trigger clock inputs that allows infinite rise and fall times.
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Re: WTF am I doing wrong with this sub osc circuit

Post by guest »

if you have a function generator, hit it with that instead of the transistor circuit to see if its output impedance being 50k is the issue. the 4013 is clocked on the rising edge, which is when the transistor lets go of the resistor, so there is only 50k there pulling it up. the /Q pin is right next door, so you might get 5pF of coupling between those two pins without any wires attached, which means a ~250ns pulse, which is more than enough to cause a second clock pulse to occur. this only happens on /Q falling, so /Q ends up staying high as it always reclocks itself to this state. you can stiffen the input signal source impedance, or add a delay from /Q to D. so a resistor from 13 to 9, a cap on 9, or both.
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Re: WTF am I doing wrong with this sub osc circuit

Post by devinw1 »

You can also try making that 68k on the inverter smaller like 10k. And also as mentioned you can square up the input even better with a past schmitt trigger inverter. It might just be the rise time is not clean and fast enough.
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Re: WTF am I doing wrong with this sub osc circuit

Post by Altitude909 »

what brand 4013 are you using? a lot of those subosc circuits only work with certain 4013s. I ran into this with the 810 where it wouldnt work with TI parts. Using toshiba solved it.. 810 uses the same sub osc circuit as 101 and 202.

the toshiba is probably the only one that will be reasonable to find in through hole. Surface mount i tried all the 4013s and half worked, half didnt :despair: i couldnt pin down what was different
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Re: WTF am I doing wrong with this sub osc circuit

Post by Synthiq »

Altitude909 wrote: Fri May 13, 2022 5:23 pm what brand 4013 are you using? a lot of those subosc circuits only work with certain 4013s. I ran into this with the 810 where it wouldnt work with TI parts. Using toshiba solved it.. 810 uses the same sub osc circuit as 101 and 202.

the toshiba is probably the only one that will be reasonable to find in through hole. Surface mount i tried all the 4013s and half worked, half didnt :despair: i couldnt pin down what was different
The Toshiba part has a Schmitt-trigger clock input.
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Re: WTF am I doing wrong with this sub osc circuit

Post by JanneI »

Just ditch the TR1 and use a square wave for an input signal, then all of those 4013 will work just fine.
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Re: WTF am I doing wrong with this sub osc circuit

Post by Altitude909 »

Synthiq wrote: Fri May 13, 2022 7:19 pm
Altitude909 wrote: Fri May 13, 2022 5:23 pm what brand 4013 are you using? a lot of those subosc circuits only work with certain 4013s. I ran into this with the 810 where it wouldnt work with TI parts. Using toshiba solved it.. 810 uses the same sub osc circuit as 101 and 202.

the toshiba is probably the only one that will be reasonable to find in through hole. Surface mount i tried all the 4013s and half worked, half didnt :despair: i couldnt pin down what was different
The Toshiba part has a Schmitt-trigger clock input.
Interesting. Is this mentioned somewhere in the data sheet? I've poured over those looking for the difference.. Reading through OP again, that's the problem for sure. Using the "wrong" part in the circuit does exactly what he is describing

edit*

"All inputs are protected by
CMOS protection network"

Is that it? (from the CD4013 data sheet)
Last edited by Altitude909 on Sat May 14, 2022 5:28 am, edited 1 time in total.
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Re: WTF am I doing wrong with this sub osc circuit

Post by flagada »

I also had issues with this circuit. It finally worked when I used an opamp in comparator configuration at the clock input.
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Re: WTF am I doing wrong with this sub osc circuit

Post by JanneI »

Scope the clock input (TR1 collector) and compare it to the modern 4013 datasheet. The input signal is not fast enough. The reason why they used it with the SH-101 this way has to do with the phases while summing the rising saw of 3340 and the sub osc.

ps. We modded the first edition of Black Corporations DIY Kijimi, which had this exact problem. Sub-osc was unreliable, especially with bass freqs. Bypass the TR1 and connect the 3340 square out directly to the clock input of the 4013 and all is well.
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Re: WTF am I doing wrong with this sub osc circuit

Post by guest »

Altitude909 wrote: Sat May 14, 2022 5:05 am Interesting. Is this mentioned somewhere in the data sheet? I've poured over those looking for the difference.. Reading through OP again, that's the problem for sure. Using the "wrong" part in the circuit does exactly what he is describing

edit*

"All inputs are protected by
CMOS protection network"

Is that it? (from the CD4013 data sheet)
the philips and toshiba datasheets show a schmitt trigger gate in their schematic diagram of the chip, whereas TI and fairchild do not. the old fairchild datasheet actually gives you the transistor layout, which doesnt have any schmitt trigger action. TI datasheet lists 5us max rise time whereas some of the others dont list this at all. this sort of thing always suprises me, when exact same part number ics behave differently. well, i guess suprise isnt the right word at this point, maybe disappoint?
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Re: WTF am I doing wrong with this sub osc circuit

Post by Synthiq »

Altitude909 wrote: Sat May 14, 2022 5:05 am
Synthiq wrote: Fri May 13, 2022 7:19 pm
Altitude909 wrote: Fri May 13, 2022 5:23 pm what brand 4013 are you using? a lot of those subosc circuits only work with certain 4013s. I ran into this with the 810 where it wouldnt work with TI parts. Using toshiba solved it.. 810 uses the same sub osc circuit as 101 and 202.

the toshiba is probably the only one that will be reasonable to find in through hole. Surface mount i tried all the 4013s and half worked, half didnt :despair: i couldnt pin down what was different
The Toshiba part has a Schmitt-trigger clock input.
Interesting. Is this mentioned somewhere in the data sheet? I've poured over those looking for the difference.. Reading through OP again, that's the problem for sure. Using the "wrong" part in the circuit does exactly what he is describing

edit*

"All inputs are protected by
CMOS protection network"

Is that it? (from the CD4013 data sheet)
There are two indicators in the datasheet, the logic diagram and the electrical characteristics:
TC4013-Sch.gif
TC4013-Sch.gif (18.22 KiB) Viewed 151 times
TC4013-Timing.gif
TC4013-Timing.gif (4.33 KiB) Viewed 151 times
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Re: WTF am I doing wrong with this sub osc circuit

Post by devinw1 »

I was also going to suggest just using the pulse straight out of the 3340. This pin actually is just a comparator for the sawtooth and a PWM voltage, so adding a comparator on the saw tooth as in input to the sub octave is doubling up on something that's already there.
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Re: WTF am I doing wrong with this sub osc circuit

Post by Synthiq »

The only issue I see with using the PWM output is that it can be set to 0% in which case you loose the sub-octave output.
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Re: WTF am I doing wrong with this sub osc circuit

Post by Altitude909 »

Synthiq wrote: Sat May 14, 2022 12:48 pm ..
There are two indicators in the datasheet, the logic diagram and the electrical characteristics:
TC4013-Sch.gifTC4013-Timing.gif
Max rise time is the same for both devices (CD4013)

diagram is different:

two parts with different logic but with the same part number. Nice. There was some other 4000 series that was like this too in some other project
cd4013.png
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